#ifndef _PC_H
#define _PC_H

#include "CPU.h"
//#include "Graphic.h"
#include "PCIe_Root_Complex.h"
#include "PCIe_Switch.h"
#include "PCIe_SATA_Controller.h"
#include "SDRAM_DDR_device.h"
#include "SDRAM_DDR_DP_device.h"
#include "DDR_SSD.h"
#include "SATA_SSD.h"
//#include "NAND_flash.h"
#include "NAND_device.h"

const unsigned	RUN_TIME		= 900;	// microseconds(us)

const unsigned	SYSTEM_TYPE		= 4;	// 1, 2, 3, 4 (South Bridge, North Bridge, North Bridge with Dedicated Path, South Bridge with Dedicated Path)
const unsigned	EXPERIMENT_TYPE	= 1;	// 1, 2, 3, 4 (sequential, page-fault, multi-task, real trace)
const unsigned	DMA_SIZE		= 16;	// 1, 4, 16 (4KB, 16KB, 64KB)
const unsigned	DMA_COMMAND		= 0xC8;	// 0xCA, 0xC8 (DMA WRITE, DMA READ)

const double	CPU_FREQ	= 1066;
const double	DRAM_FREQ	= 400;
const double	SATA_FREQ	= 300/4;
const double	FLASH_FREQ	= 75;

const unsigned	DRAM_MEM_START_ADDRESS_UNDER_4G		= 0x0;
const unsigned	DRAM_MEM_END_ADDRESS_UNDER_4G		= 0x7FFFFFFF;	// 2GB
const unsigned	DRAM_IO_START_ADDRESS				= 0x80000000;
const unsigned	DRAM_IO_END_ADDRESS					= 0x8FFFFFFF;	// 250MB
const unsigned	DRAM_CONF_START_ADDRESS				= 0x90000000;
const unsigned	DRAM_CONF_END_ADDRESS				= 0x9FFFFFFF;	// 250MB

const unsigned	DMI_MEM_START_ADDRESS_UNDER_4G		= 0xA0000000;
const unsigned	DMI_MEM_END_ADDRESS_UNDER_4G		= 0xDFFFFFFF;	// 1GB
const unsigned	DMI_IO_START_ADDRESS				= 0xE0000000;
const unsigned	DMI_IO_END_ADDRESS					= 0xEFFFFFFF;	// 250MB
const unsigned	DMI_CONF_START_ADDRESS				= 0xF0000000;
const unsigned	DMI_CONF_END_ADDRESS				= 0xFFFFFFFF;	// 250MB

const unsigned	DRAM_MEM_START_ADDRESS_OVER_4G_HIGH	= 0x1;
const unsigned	DRAM_MEM_START_ADDRESS_OVER_4G_LOW	= 0x0;
const unsigned	DRAM_MEM_END_ADDRESS_OVER_4G_HIGH	= 0x2;
const unsigned	DRAM_MEM_END_ADDRESS_OVER_4G_LOW	= 0x7FFFFFFF;	// 6GB

const unsigned	DMI_MEM_START_ADDRESS_OVER_4G_HIGH	= 0x2;
const unsigned	DMI_MEM_START_ADDRESS_OVER_4G_LOW	= 0x80000000;
const unsigned	DMI_MEM_END_ADDRESS_OVER_4G_HIGH	= 0xF;
const unsigned	DMI_MEM_END_ADDRESS_OVER_4G_LOW		= 0xFFFFFFFF;	// 54GB

const unsigned	SATA_MEM_START_ADDRESS_UNDER_4G		= 0xA0000000;
const unsigned	SATA_MEM_END_ADDRESS_UNDER_4G		= 0xDFFFFFFF;	// 1GB
const unsigned	SATA_IO_START_ADDRESS				= 0xE0000000;
const unsigned	SATA_IO_END_ADDRESS					= 0xE7FFFFFF;	// 125MB
const unsigned	SATA_CONF_START_ADDRESS				= 0xF00FA000;
const unsigned	SATA_CONF_END_ADDRESS				= 0xF00FAFFF;	// 4KB

const unsigned	SATA_MEM_START_ADDRESS_OVER_4G_HIGH	= 0x3;
const unsigned	SATA_MEM_START_ADDRESS_OVER_4G_LOW	= 0x0;
const unsigned	SATA_MEM_END_ADDRESS_OVER_4G_HIGH	= 0x6;
const unsigned	SATA_MEM_END_ADDRESS_OVER_4G_LOW	= 0xFFFFFFFF;	// 16GB

const unsigned	SOUTH_MAIN_DMA_PRD_START_ADDRESS	= 0x4000000;
const unsigned	SOUTH_SSD_DMA_PRD_START_ADDRESS		= 0x5000000;
const unsigned	NORTH_MAIN_DMA_PRD_START_ADDRESS	= 0x6000000;
const unsigned	NORTH_SSD_DMA_PRD_START_ADDRESS		= 0x7000000;

const unsigned	NORTH_DMA_COMMAND_REG_START_ADDRESS	= 0x7E000000;
const unsigned	NORTH_DMA_CHECK_REG_START_ADDRESS	= 0x7C000000;

const unsigned	SOUTH_DMA_COMMAND_REG_START_ADDRESS	= 0xD0000000;
const unsigned	SOUTH_DMA_CHECK_REG_START_ADDRESS	= 0xD2000000;

#endif
